Generally, it is necessary to test the electrical characteristics of a semiconductor device, such as the integrated circuit devices at the wafer level, to check whether the integrated circuit device meets product function and breakdown specifications. Integrated circuit devices with electrical characteristics meeting the specifications are selected for the subsequent packaging process, while other devices are discarded to avoid additional packaging cost. Other full function electrical tests are performed on the integrated circuit device after the packaging process is completed so as to screen out substandard devices and guarantee product quality. In other words, during fabrication of an integrated circuit chip, multiple tests for electrical properties have to be performed.
FIG. 1 shows a testing system 10 for testing a device under test (DUT) 31 (for example, a semiconductor device) according to the prior art. The testing system 10 includes a housing 11 (for defining a testing chamber 13), a stand 17 disposed in the housing 11, a base 30 disposed on the stand 17 for receiving the DUT 31, a head plate 15 (having an opening 19) disposed on the housing 11, and a probe card 40 disposed on the head plate 15. The DUT 31 is disposed on the base 30 with a heater 33.
The probe card 40 includes a circuit board 41, a supporter 45 disposed on the circuit board 41, and a plurality of probes 43 fixed on the supporter 45 with epoxy resin 47. The circuit board 41 has a first surface 42A and a second surface 42B, and a front end of a probe 43 and the DUT 31 facing the second surface 42B can form an electrical connection. A rear end of a probe 43 is electrically connected to a wiring 53 on the first surface 42A of the circuit board 42 through a conductive channel 51 inside the circuit board 41. During the test, the base 30 is raised so as to form an electrical contact between the front end of the probe 43 and a pad 35 of the DUT 31 such that an electrical connection is established between the probe card 40 and the DUT 31. During the test, a testing signal is transmitted to the DUT 31 through the probe 43 of the probe card 40, and a response signal of the DUT 31 is transmitted outside of the probe card 40 through the probe 43 for further analysis so as to implement the electrical property test of the DUT 31.
When a failure occurs on the probe card 40 and the probe card 40 has to be replaced, in the prior art, the whole probe card 40 has to be disassembled from the testing system 10, checked, repaired and reassembled to the testing system 10, and then the test can be re-performed. For example, even if only a part of the probes 43 are worn due to long-term use and have to be replaced, in the prior art, the whole probe card 40 has to be dissembled from the testing system 10, checked, repaired and reassembled to the testing system 10, and then the test can be re-performed. This process is obviously time-consuming. In addition, the location of the probe 43 of the probe card 40 has to be correspondingly adjusted according to different types of the DUT 31. In the prior art, the whole probe card 40 has to be dissembled from the testing system 10, a new probe card 40 is reassembled to the testing system 10, and then the test can be re-performed. Such process is obviously time-consuming as well.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.